Vendor Updates

SK hynix showcased 12-layer 36GB HBM4 and SOCAMM2 memory modules built for Nvidia's Vera Rubin superchip.

They claim combining Cerebras wafer-scale chips with GPUs will deliver up to 3,000 tokens per second for AI inference workloads.

The facility is co-located with 531 MW of wind generation and uses a closed-loop, non-evaporative liquid cooling system.

AMD agreed to buy AI startup World Labs in an $8.2 billion all-stock deal to help shape its future AI hardware and software roadmaps.

The company will build an AI cloud facility in Mayes County with closed-loop cooling and expects to generate $500 million in local taxes over ten years.

The repository indexed recent work on Triton kernel optimization, NVIDIA Blackwell confidential computing, and multi-GPU parallelism.

The 256-qubit system will link directly to an Nvidia GB200 NVL72 cluster over NVQLink next year.

CINECA says AI now makes up over half of Leonardo's workload, driving a shift to multi-protocol data platforms across its clusters.

Each 72-GPU rack provides 20.7 TB of HBM4 and 216 TB/s of NVLink bandwidth across 18 compute trays with direct liquid cooling.

SemiAnalysis gave CoreWeave its top cluster rating again, citing custom tools for straggler detection, node validation, and GPU testing.

They added local-latency cross-region writes to reduce checkpoint pauses when training on distributed GPU clusters.

LG says its 2.6 MW liquid-cooling unit met Nvidia DSX reference design requirements for dense AI server clusters.

VAST says DataEnclave runs AI workloads across encrypted CPU and GPU memory without exposing weights or data to infrastructure operators.

They claim a single GB300 NVL72 rack reached over 1.16 million tokens per second running GPT-OSS-120B in server mode.

SK hynix executives discussed their HBM roadmap and expansion of production hubs in Korea and the US to meet AI memory demand.

CoreWeave detailed its automated lifecycle tools for managing liquid cooling, power, and firmware across multi-rack Nvidia Vera Rubin NVL72 clusters.

Rambus says its new hardware security block runs alongside an unmodified open-source Caliptra core to preserve trademark eligibility.

PrefixBench-H100 evaluates vLLM and TensorRT-LLM on H100 GPUs to map where KV-cache prefix reuse lowers first-token latency and where cache pressure erodes it.

They claim the GPU-optimized ML force field scales at O(N) instead of O(N³) to replace costly DFT in semiconductor material design.

They presented High Bandwidth Flash NAND and AiMX processing-in-memory accelerator cards designed to reduce memory bottlenecks in AI inference.

The multi-year deal increases Vermont fab capacity for 200G-per-lane SiGe chips used in optical transceivers and co-packaged optics.

The funding round values Crusoe at $30.9B as they expand power generation, modular data center builds, and cloud capacity for AI workloads.

Users can now cancel or terminate up to 50 individual or array jobs in a single API call across all AWS Batch regions.

The group aims to standardize how AI data centers adjust electricity demand in real time to speed up power grid interconnections.

Samsung says the E3.S drive hits 245.76TB with 4.5 GB/s sequential writes and a 0.6 drive writes per day endurance rating.

They claim the controllers double bandwidth over prior parts and improve inference time to first token by up to 62% using fabric-attached memory.

They ran a Gemma model using ROCm 10 on a 32-core P870-D host offloading inference to AMD Radeon AI PRO R9700 GPUs.

Micron says the TSV-stacked modules enable up to 12TB per dual-socket server and cut operating power by over 60% compared to four 128GB DIMMs.

They claim the controllers double memory bandwidth and cut time to first token by up to 62% in AI inference workloads.

Nvidia added CUDA-Q Logical to its hybrid quantum platform, which Fermilab claims sped up fault-tolerant architecture exploration by 7x.

The AI cloud provider agreed to principles requiring data center builders to cover their own power use and protect local electric grids.

DDN says its parallel storage platform currently supports over one million GPUs in AI and supercomputing environments.

They found diffusion models boost arithmetic intensity via parallel tokens but lag autoregressive models on long contexts and batched throughput.

The container tests control plane health, GPU availability, network policies, and storage drivers on clusters running NVCF workloads.

They claim the step-level speculative decoding framework cuts LLM reasoning inference latency by up to 2x at matched accuracy.

Researchers say pretraining an enlarged 2.8B model and pruning it to 1.3B across 2T tokens beats training the target size from scratch.

They found scarce target corpora can be reused 15 to 20 times during mixture pretraining before hitting diminishing returns.

At events in China, Arm highlighted cloud options like Neoverse CSS N4 alongside profiling tools to help engineers deploy AI models across edge and cloud.

SK hynix executives met with AI leaders to discuss shifting workload demands and future directions for memory development.

They offer 24-hour turnaround on bulk inference jobs for models like Llama 3.3 70B at a 25% discount off on-demand rates.

They announced Neoverse CSS N4 for scale-out servers alongside a new AGI CPU designed for datacenter AI infrastructure.

Samsung invested in Mistral AI to develop on-premises models tailored for semiconductor design, defect prediction, and fab optimization.

The tutorial covers NCCL device APIs for PyTorch workloads and provides companion code exercises on GitHub.

The hub provides pre-optimized AI models for Arm silicon, claiming over 4x speedups for models like Qwen3-TTS using SME2 vector extensions.

The companies say they will develop custom AI inference silicon and optical interconnects running up to 1.6T for AWS data centers.

They will integrate Qoro's software with Hartree's Slurm scheduler via QRMI to build hybrid quantum-classical chemistry workflows.

Arm claims the N3P-based subsystem scales up to 128 cores at 3.8 GHz with a 2x speed boost over the previous generation.

They introduced cuda-oxide for SIMT kernels via a custom codegen backend and cutile-rs for tile-based GPU programming on stable Rust.

Samsung led Mistral's Series D round and plans to run custom models on-prem for defect detection and equipment tuning in its fabs.

Samsung is putting half its 4nm capacity toward HBM4 base dies to handle custom logic like on-die memory controllers and PHYs.

Intel says it has processed over one million wafers with High-NA EUV tools across R&D and production layers for Panther Lake chips.

Samsung says it will adopt ASML's High NA EUV lithography for mass DRAM production by 2028 and back a move to 12-inch photomasks.

The resource hub compiles Samsung Foundry sessions and blogs covering 3D chip packaging, process nodes, and semiconductor partnerships.

DDN will highlight its Infinia storage platform designed to keep GPU clusters saturated at the ALL IN summit in Montreal.

VAST says its NVMe/TCP block driver can handle millions of devices per system with automatic host pruning and multi-tenancy for AI workloads.

Jensen Huang says the deal covers purchase price plus retention awards and is subject to regulatory approval.

The session will compare how DDN Lustre, IBM Storage Scale, VAST Data, and Weka handle high-throughput HPC and AI workloads on Google Cloud.

SK hynix displayed server memory products including HBM4, a 128GB MRDIMM, and a liquid-cooled enterprise SSD at Dell Technologies Forum.

IBM says a single 4U Storage Scale System 6000 reaches up to 330 GB/s throughput and 13 million IOPS with GPUDirect Storage support.

The vendor newsroom highlights interconnect deployments on supercomputers at LLNL and TACC alongside partnerships with NEC, AMD, and NextSilicon.

The $500 million site uses Dell servers with Nvidia Blackwell GPUs, and the company plans to eventually scale capacity past 400 megawatts.

They project scaling DeepSeek-R1 to 256 RDUs delivers 500 tokens per second while maintaining 45% model bandwidth utilization.

Oracle plans to deploy HPE Juniper routing and switching gear across its cloud data centers to support large-scale AI infrastructure.

Crusoe says the 5 GW battery setup buffers rapid GPU power swings and keeps clusters online during grid voltage drops.

Arm noted that Neoverse N2 upgrades DC IVAC to DC CIVAC and flushes dirty system-level cache lines out to main memory.

Intel says Diamond Rapids will pack up to 256 cores and 16 memory channels, while Crescent Island offers 480GB of LPDDR5X in a 350W card.

They claim vertically stacking HBM directly onto processors using copper bonding boosts bandwidth and cuts the energy required for data movement.

The update adds tools for managing and operating production AI infrastructure, the company says.

They claim their Slurm on Kubernetes stack reaches up to 96% training goodput on Hopper and improves mean time to failure by about 10x.

Microsoft opened preview access for its Cobalt 200 Arm VMs, claiming a 50% performance boost for Linux-based AI workloads.

The company showed 16-layer 48GB HBM4 and 12-layer HBM4E, while proposing High Bandwidth Flash to sit between HBM and SSD tiers.

The updated specification defines formulas for 10 metrics tracking branch mispredictions, TLB walks, and cache misses per thousand instructions.

They showed 18A-based Xeon 6+ processors and new rack systems pairing Xeon CPUs with SambaNova SN-50 RDUs for inference.

The 8U chassis pairs dual AMD EPYC 9005 CPUs with eight MI355X OAM accelerators and twelve 3,000 W power supplies.

They claim pipelining the unquantized model across CS-3 wafer systems hits 750 tokens per second by keeping weights in local SRAM.

He notes Cori's DataWarp burst buffer saw only 15% utilization despite a 2x I/O boost, and Gordon dropped from 32 planned vSMP nodes to just two.

The company updated its press kit with photos and datasheets for its CS-3, CS-4, and Wafer-Scale Cluster systems.